Conroe, Conroe, Conroe. Since the spring Intel Developer Forum (IDF), that is all we've heard people talking about when the conversation turns to CPUs. But what do you really know about the Conroe core? What is it's underlying microarchitecture? What is a microarchitecture, for that matter? How did Intel come up with this one? This article will help you answer those questions. The third question is the easiest to answer. A microarchitecture, commonly called a 'marchitecture', is a basic design that processors for that generation will use when their respective cores are designed. It's like a mother-core. For example, the mother of the Prescott, Presler, Northwood, Prestonia, Willamette, and Nocona cores is NetBurst. A marchitecture is not easy to design and AMD and Intel create a new one only once ever couple of years. The name of the marchitecture that Intel is using to create Conroe is called Intel Core Microarchitecture, or ICM. It will be the first new marchitecture since the Pentium III was replaced by the Pentium 4. Too see how ICM started out, it's time to take a trip back in time. Hang on!

The year is 2003. AMD as just released their cutting-edge Athlon 64 chips with a whole new marchitecture, dubbed “K8”. It is received to rave reviews, and even Intel's monstrous PR machine can't keep consumers from buying stores out of stock. Deep inside Intel's HQ, the best and brightest are coming to a realization: They're in trouble. They've seen first-hand what a first-generation Athlon 64 can do to their fully developed, top of the line Pentium 4 chips, and it isn't pretty. They also know that the next generation of Pentium 4 processors, currently codenamed Tejas and Jayhawk, are having serious heat trouble. If their researchers couldn't get those issues resolved, then they'd have to execute plan B: multiple cores. Fast forward to May, 2004, and plan B becomes a reality. Tejas and Jayhawk have been terminated, and single core development is effectively banned to a side project. Quickly into dual-core development it became apparent that the Pentium 4, between it's obtrusively long pipeline and it's high heat dissipation, was never meant to be a multiple-core chip. Finally, the heads realized the obvious: They had to start over from square one, designing an x86 marchitecture from the ground up that would be radically different from any ever seen before. It was to be called Intel Core Microarchitecture.

In order for Intel to design the ICM properly, they examined the advantages of shortcomings of both the Netburst (Pentium 4) core design and the P6 (Pentium III and Pentium M) cores. To create the ultimate processor to overthrow the power of AMD's chips, they needed the best of both worlds from these designs. So where, exactly, did that leave Intel? The answer to this question lies in looking at the same to marchitectures that they looked at, the P6 and NetBurst.

P6

The 80686 marchitecture, or P6 for short, was for the Pentium Pro, Pentium II, Pentium III, and Pentium M processors. It's original use in the Pentium Pro was as a high-power enterprise alternative to the 80586-based processors, known as the original Pentium. Once the limits of the Pentium were realized, P6 hit prime time with the release of the Pentium II. The P6-era of desktop computing lasted 5 years until 2000, with the release of the Pentium 4. P6 has come back in recent years when it was discovered to be a viable alternative to the power-hungry Pentium 4.

The 80686 design is based on a 10-14 stage instruction pipeline. Using a pipeline of this length, the various different P6-based cores can achieve impressive efficiency per clock cycle, using a very low amount of power. This solution was ideal both in the past, when modern methods of increasing a CPU's power dissipation weren't available, and now, in situations where power is in limited supply, such as laptops. Additionally, the P6 was capable of incredible integer calculation scores, owing to it's multiple arithmetic logic units (ALU s) within the core itself.

On the other hand, the P6 was not without problems. For starters, it had horrendous floating-point scores, mainly due to the presence of only a single floating point unit (FPU) on the core. Another major disadvantage was the limit the marchitecture put on bus speeds. Even with the greatest P6 ever created, the dual-core Yonah, the front side bus speed is only 667MHz. This is over 100MHz shy of the 800MHz FSB that Pentium 4's achieved years ago. With such a small bus frequency, the bandwidth with the memory of a system was severely limited.

The P6 was a well made design, but it's crippling limitations kept it from being any sort of competition to the AMD K8. Some of it's more interesting features, however, were noted, and the researchers turned their eyes to their baby from only 5 years ago, the NetBurst.