NetBurst

There is no such thing as the 80786 or P7. It is officially called NetBurst. Whatever you call it, it was the desktop replacement for the P6. NetBurst was born and bred to be centerpiece of a PR campaign. The campaign was to create and foster a media “gigahertz war” and then win that war handily. While the PR division was busy creating this war, the research division was busy designing it's only troop.

The key to winning the war was scalability. Whatever design the engineers came up with, it had to be able to reach very high frequencies. The key to achieving much higher frequencies than before with no new increase in production technologies was in the pipeline of the marchitecture. By increasing the pipeline's size to unheard-of stages, the chip's overall efficiency would be reduced and therefore be capable of higher frequencies. Intel didn't want to lose to much bang for the buck with these higher clock speeds, so they invested large amounts of research into improving the pipeline's branch predictors. As clock speeds increased on the chips, so did bus speeds. The latest and last generation of NetBurst processors are capable of supporting a 1066MHz front side bus, which is nearly twice that of the latest P6's. Though still not a fully effective memory interface design, it was certainly a lot better than that of the P6.

The original plan was to scale the NetBurst up to 10 GHz. This was not to be, however. The problem that kept appearing was one of heat. Ever successively faster P7 chip was also much hotter than it's predecessor. Intel tried to remedy this by expanding P7's original 20 stage pipeline to 31 stages with the introduction of the Prescott core, but it had even more temperature problems. Due to this problem, Intel canned any future single-core NetBurst plans, including their much-anticipated Tejas and Jayhawk cores. The dying gasp of NetBurst was it's life as a dual core processor. The less said about this iteration the better. The only manner with which these two cores could communicate was through the front side bus, which it shared with the memory interface. The bottlenecks weren't pretty.
NetBurst was a huge PR victory for Intel, but AMD was not to be outdone. It made a massive resurgence with the release of it's own next-generation marchitecture called K8, and it left NetBurst in the dust, regardless of what the gigahertz were. NetBurst was put in the shop and stripped for parts.

Intel Core Microarchitecture (ICM)

As the reader may well already realize, the benefits and problems of P6 compared to NetBurst almost completely complement each other. Where one has a disadvantage, the other has an advantage, and vice-versa. Of course, some of these specifications are mutually exclusive, such as pipeline length, but others where easy to change with a simple marchitecture revamping. Along with combining several great features from the past, some new innovations were included to keep the design up to date with modern times.


The elements borrowed from the P6 center mostly around the pipeline of the chip. ICM uses a relatively short 14-stage pipeline, which is similar to that of the P6's 10-14 stages. Combining that efficient of a pipeline with the effectiveness of NetBurst's branch predictor creates a very powerful starting point for ICM. Another carry-over from the P6 was the low power consumption. ICM will supposedly use almost half the wattage that an equally powerful NetBurst-based CPU would. An innovation taken from NetBurst is the high bus speeds that came to dominate that design. ICM chips will start out at 1066MHz front side bus, and easily scale to 1333MHz and beyond. It will also incorporate the various heat dissipating technologies that Intel developed to counter NetBurst's hot head. On the more efficient ICM, this translates to relatively high clock speeds, considering the length of the pipeline.

The main part of ICM that Intel had to make from scratch was how it would work in a multi-core setup. Unlike the K8 from AMD, NetBurst was never designed with something like that in mind and therefore it's implementation was haphazard. ICM looks to rectify this. Now the two cores won't communicate through the bus, but through their own cache. Each core will be connected to 2-4MB of shared L2 cache, and their L1 caches will be linked as well, allowing for massively fast data transfer between the cores. To further add to the efficiency of ICM, the design will feature a 4-issue core as opposed to a 3-issue core, and it will incorporate “Macro-ops fusion”, which is marketing speak for a technology that allows ICM to execute two select x86 instructions per cycle instead of one. Finally, it will be able to calculate SSE instructions twice as fast.

The ICM will be Intel's first totally new design in over 6 years, and it will be the conclusion of lessons learned over the last 15 years. Preliminary benchmarks, though Intel-sponsored, showed engineering samples of these new chips absolutely dominating the latest K8 offerings. Set to debut in only a few months, they should reach our computers by the time fall comes around. When that happens, time will only tell what the future of both chip companies will be. However, for now, one can say this: Intel was taught a lesson by AMD on complacency, and the way this architecture is shaping up, Intel appears to have learned that lesson... and many, many others over the years.